1. Field of the Invention
The present invention relates to memory cells in an integrated circuit. More specifically, the invention relates to using a standard transistor as a flash/dynamic random access memory (DRAM) in order to reduce the size of a gate oxide for a memory cell in an integrated circuit.
2. Background
FPGA integrated circuits are known in the art. Typically, an FPGA has an array of logic elements and wiring interconnections with many thousands of programmable interconnect cells so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable interconnect cell, or switch, can connect two circuit nodes in the integrated circuit to make or break a wiring interconnection or to set the function or functions of a logic element.
FPGA devices may be classified in one of two categories. One category of FPGA devices is one-time programmable and uses elements such as antifuses for making programmable connections. The other category of FPGA devices is reprogrammable and uses devices such as transistor switches as the programmable elements to make non-permanent programmable connections.
Reprogrammable FPGA devices include some means, such as static random access memory and dynamic random access memory, for storing programming information used to control the programmable elements. Non-volatile memory devices such as EPROMs, EEPROMs, non-volatile RAM, and flash memory devices have all been proposed for or used to store programming information in the class of FPGA applications.
An ideal memory device optimizes density, preserves critical memory in a nonvolatile condition, is easy to program and reprogram, and is read quickly. Some non-volatile memory devices meet more of the above requirements than others. For instance, EPROMS are high density, however, they have to be exposed to ultra-violet light for erasure. EEPROMS are electrically byte-erasable, but are less reliable and have the lowest density. Flash memory devices, however, are low-cost, high-density, low-power, high-reliability devices resulting in a high-speed architecture.
FIG. 1 is a simplified schematic diagram of a flash memory cell. Flash memory cell 100 comprises a sense transistor 102 and a switch transistor 104. Sense transistor 102 is usually a smaller, minimum-geometry device used for programming. Switch transistor 104 is a larger-geometry device, a pass transistor switch element is used to selectively connect two nodes 116 and 118 in the integrated circuit. Electronically, floating gate 110 is shared by both programming transistor 102 and switch transistor 104. Programming is accomplished with Fowler-Nordheim tunneling. Fowler-Nordheim tunneling is well known in the integrated circuit art and will not be discussed herein to avoid overcomplicating the disclosure and thereby obscuring the present invention.
FIG. 2 is a simplified top-level layout view of the flash memory cell of FIG. 1. As in FIG. 1, flash memory cell comprises a switch transistor 202 and a sense transistor 204.
However, a flash memory transistor cannot be easily scaled with the rest of the process. As is well known to those of ordinary skill in the art, the gate oxide of a flash memory transistor is thick, on the average of 8.5 nm. The CMOS process technology to date provides a junction capacitance of not lower than 1 ff. A flash memory cell with a lower capacitance is impractical.
Hence, there is a need in the art for a memory cell that can scale with the rest of the integrated circuit. There is also a need for a memory cell that has a junction capacitance of lower than 1 ff.